{"id":136,"date":"2026-04-03T17:38:57","date_gmt":"2026-04-03T17:38:57","guid":{"rendered":"https:\/\/mrsdprojects.ri.cmu.edu\/2026teamf\/?page_id=136"},"modified":"2026-05-02T15:27:12","modified_gmt":"2026-05-02T15:27:12","slug":"pcb-design","status":"publish","type":"page","link":"https:\/\/mrsdprojects.ri.cmu.edu\/2026teamf\/system-summary\/pcb-design\/","title":{"rendered":"PCB Design"},"content":{"rendered":"

PCB Concept<\/h3>\t\t\t

The PCB for Version 1 of the FireSense payload focused on power distribution and system debug information, and the final assembled version can be seen above. Below is the last conceptual design before moving forward with schematic development.<\/p>\n

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The payload is powered by an 18V battery, and so a PCB is needed to step down this voltage to 12V and 5V from a variable voltage between 15V and 21V (overcharged\/undercharged battery). This is achieved through two RT7258GSP buck converters each configured for 12V and 5V outputs respectively. The 12V rail powers the Nvidia Jetson Orin AGX and two fans used to cool the Boson+ Thermal Cameras. The 5V rail powers the radar, radar capture card, and the LED debug panel.<\/p>\n<\/div>\n\t\t<\/div>

PCB Schematic<\/h3>\t\t\t

The PCB was designed using Altium Professional Student License. We began by creating the schematic of our circuit. To do this effectively we needed to also have an in-depth understanding of the components that we would use. The strategy followed was to primarily design around the RT7258GSP buck converters, selecting the necessary resistors and inductors for proper function. Bulk & decoupling capacitors were added to stabilize the output of the signal.
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The debug board and functionalities of the PCB were then added, whith a UART pinout for each Thermal Camera and an array of 3 different color LEDs for programmable debugging.<\/p>\n<\/div>\n\t\t<\/div>

PCB Layout creation in Altium<\/h3>\t\t\t

The layout of the PCB can be seen below. The red is the top layer routes, and the blue is the bottom layer power route and copper pour. When designing the board, there were a few considerations:<\/p>\n

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  • Minimize right angle traces<\/li>\n
  • Adjust trace widths to ensure the traces can handle the current on its respective lines<\/li>\n
  • Add enough vias for the current –> ground<\/li>\n
  • Avoid the electromagnetic fields of the inductors<\/li>\n
  • Group debug features together to form the proper area for a debug panel<\/li>\n<\/ul>\n

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    PCB 3D render of Layout<\/h3>\t\t\t

    Through an online library called SnapEDA, we were able to procure many of the footprint and 3D models of many of the components. These models are able to be rendered in Altium, and so we are able to visualize the 3D space that the components take up on the board to avoid overlap. The front and back of this 3D render of the PCB layout can be seen below:
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    PCB Assembly<\/h3>\t\t\t

    The assembly of the board was primarily conducted with thermal solder paste and a heat gun. This trivialized the surface mount assembly process compared to soldering with an iron. For the through hole components, the traditional approach with a solder iron was used in conjunction with plenty of solder flux. The photo below shows the assembly workstation. Pardon the poor ESD protections, as the PCB lab’s ground pads had been covered in solder paste and there was serious concern about bridging. This board is one of three, and so on future assemblies a better & cleaner mat will be used.
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    PCB Bench Test and System Test<\/h3>

    \n When testing the PCB on the lab bench, it was successful in stepping down a range of 15 V to 21 V from the DC power supply to a very stable 12.26 V and 5.03 V across its two power lines. However, when the PCB was integrated into the payload, the buck converters caught fire. While the exact cause of this critical failure is still unknown, the leading theory is the lack of surge protection from the battery. When a fully charged 18 V battery is connected to the circuit, the energy rushes in and slams against the capacitors, creating an LC resonant circuit. This can cause the voltage to “ring,” overshooting to double the battery’s resting voltage (potentially spiking to 40 V+ for a microsecond). This spike punctures the silicon in the main controller chip or the input capacitor, causing a catastrophic short. This could have been avoided with a large capacitor on the input rail to dampen this voltage spike, and the next version of the PCB will be designed with this solution, along with dimensional changes for integration with Payload 2.0.\n<\/p>\n\n\n\n\n\n